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ATmega128
Figure 79. USART Block Diagram
Clock Generator
UBRR[H:L]
BAUD RATE GENERATOR
OSC
UDR (Transmit)
TRANSMIT SHIFT REGISTER
SYNC LOGIC
PARITY
GENERATOR
CLOCK
RECOVERY
PIN
CONTROL
Transmitter
TX
CONTROL
PIN
CONTROL
Receiver
RX
CONTROL
XCK
TxD
UCSRA
RECEIVE SHIFT REGISTER
UDR (Receive)
DATA
RECOVERY
PARITY
CHECKER
UCSRB
PIN
CONTROL
UCSRC
RxD
Note:
Refer to Figure 1 on page 2 , Table 36 on page 77 , and Table 39 on page 80 for USART pin
placement.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter, and Receiver. Control registers are shared by all units.
The clock generation logic consists of synchronization logic for external clock input used by syn-
chronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only
used by Synchronous Transfer mode. The Transmitter consists of a single write buffer, a serial
Shift Register, parity generator and control logic for handling different serial frame formats. The
write buffer allows a continuous transfer of data without any delay between frames. The
Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the receiver includes a parity checker, control logic, a Shift Register and a two level
receive buffer (UDR). The receiver supports the same frame formats as the Transmitter, and can
detect frame error, data overrun and parity errors.
171
2467X–AVR–06/11
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